搜索资源列表
u26a_spice
- ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
xapp935
- ddr2 controller, verilog source code from xilinx
zbt_rd_vhdl_str_v1.0.0
- ddr2 controller功能控制,里面有四个模块
vga_control
- vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
byNeyno_
- micron data sheet for designing the ddr2 sdram controller part1
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
TMS320C6455
- tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controll
c_xapp858
- 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the i
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
the_design_and_realization_of_DDR2-SDRAM_controlle
- ddr2控制器的设计与实现,详细介绍了其结构和思想-the design and realization of DDR2-SDRAM controller
spart6_ddr2_example_source
- 这是目前比较新的平台spart6上的MCB的实例，spart6内置一个DDR2的控制器，对于需要用到新平台的朋友，有一定的帮助。-This is a relatively new platform spart6 instance on the MCB, spart6 built a DDR2 controller, need to use a new platform for friends, have some help.
DDRsdram2
- 一个DDR2 的控制器源码，它是由LATTICE的编译器生成。-A DDR2 controller source code, which is generated by the compiler LATTICE.
DDRCHv11
- Source code for ddr2 dram controller for BEEE
ddr2_sodimm_x64_333MHz_hp2
- DDR2内存条（sodimm封装）的控制器设计-DDR2 controller for sodimm
2048Mb_ddr2_verilog_model
- ddr2 verilog model,用于验证DDR2 Controller。-DDR2 Verilog model, and used to verify the DDR2 Controller.
DDDRR2_sdrramD
- DDR2 的控制器，它是由由LATTICE的编译器生成。 -DDR2 controller, which is generated by by LATTICE the compiler.
childers
- micron data sheet for designing the ddr2 sdram controller part2
DDR2standardize-Chinese-version
- DDR2规范中文版，对ddr2控制器编写十分有用-DDR2 specification Chinese version prepared ddr2 controller is very useful
VerilogHDL-DDR2SDRAM
- 关于DDR2 控制器的设计 是通过verilog语言设计-DDR2 controller design through verilog language design
design-method
- 基于Xilinx_fpga的ddr2控制器设计方法，英文版本，有注释-Based Xilinx_fpga of ddr2 controller design method, the English version, there are notes